1) Field of the Invention
The present invention relates to a pipeline operation method in which plural operational units including pipeline operational units (e.g. multipliers) and non-pipeline operational units (e.g. dividers) share a single writing port to perform an operational process. The present invention also relates to a pipeline operation device in which plural operational units including pipeline operational units (e.g. multipliers) and non-pipeline operational units (e.g. dividers) share a single writing port to perform an operational process.
2) Description of the Related Art
Generally, in order to write operation results from plural operation units into a floating-point register (hereinafter referred to as FR), there are (1) a writing method in which a FR includes writing ports corresponding to the number of operation units and the operation result from each operation unit is ready to write to the FR without controlling the writing timing, and (2) a writing method in which plural operation units share one writing port and the operation result of each operation unit is written to the FR while the writing timing is being controlled.
Today""s computers perform the pipeline operation shown in FIG. 6 for a command execution. Referring to FIG. 6, numeral 2 represents an instruction queue, 3 represents an instruction register, 4 represents a decoder (DEC), 5 represents a pipelinne control circuit, 6 represents a floating-point register (FR), and 9 represents a pipeline operation unit. The elements will be explained in detail with reference to FIG. 8.
In the pipeline operation, the following instruction is started before the previous instruction has been completed. A process which can be divided into plural steps is distributed to plural processing mechanisms corresponding to each step land subjected to a process. But datum to be processed does not pass the same processing unit plural times.
The pipeline operation, as shown in FIG. 6, is formed of an instruction selection stage Sf, a register reading stage Ff, operation execution stages E1f to Emf, and a writing stage Wf. The instruction selection stage Sf is a stage which selects an instruction. The register reading stage Ff is a stage which translates or decodes an instruction and reads data out of a register. The operation execution stages E1f to Emf are stages which execute an arithmetic operation (the case where an arithmetic operation is performed in the m-th stage, where m is the number of operation cycles (the number of operation execution stages) of the pipeline operation unit 9 in FIG. 6). The writing stage Wf is a stage which writes an operation result into a register.
In the pipeline operation, the pipeline control circuit 5 selects an instruction to be processed out of the instruction queue 2 in the first instruction selection stage Sf to write it into the instruction register 3. The decoder 4 decodes an instruction selected in the instruction selection stage Sf in the register reading stage Ff and then reads data out of the FR 6 according to the decoded result.
Thereafter, an actual operation is executed using data read out of the operation unit 9 in the operation execution stages E1f to Emf. Then the final operation result obtained in the operation execution stage Emf is written into the FR 6 in the writing stage Wf.
In the above-mentioned operation, plural stages are carried out in parallel (overlap execution) while they are shifted by one cycle (one stage). Thus in every cycle, data is input and the operation result is output. The pipeline operation unit 9 can operate the above-mentioned operation.
In addition to the pipeline operation unit 9 such as a multiplier that can perform the pipeline operation, there is a non-pipeline operation unit such as a divider which cannot operate the pipeline operation or cannot operate plural stages in parallel (overlap execution).
When the non-pipeline operation unit, as shown in FIG. 7, begins an arithmetic operation, it cannot execute the register reading stage Ff until the completion of the arithmetic operation or for (n+1) xcfx84, where n is the number of operation cycles (the number of operation execution stages) of the non-pipeline operation unit and xcfx84 is time (control period) taken for one cycle (one stage), so that the next data cannot be received. In FIG. 7, numeral 7 represents a non-pipeline operation unit.
Hence, non-pipeline operation unit cannot perform a pipeline operation as the pipeline operation unit 9.
Generally, the divider being a non-pipeline operation unit takes, much time for an arithmetic operation and has a small appearance frequency as an instruction.
As shown in FIGS. 8 and 10, generally, the non-pipeline operation unit 7 such as a divider and the pipeline operation unit 9 which can perform a pipeline operation often share the writing port 6a of the FR 6.
However, where the writing port 6a is shared, two operation units 7 and 9 cannot simultaneously execute an writing operation to the FR 6. Therefore, two methods have been conventionally used as follows:
(a) The pipeline operation unit 9 is inhibited in its operation while the non-pipeline operation unit 7 is operating.
(b) The writing stage Wf of the pipeline operation unit 9 is delayed by 1xcfx84 only when the writing stage Wf of the non-pipeline operation unit 7 is overlapped with the writing stage Wf of the pipeline operation unit 9.
The configuration of the pipeline operation device adopting the former case (a) is shown in FIG. 8. In FIG. 8, numeral 1 represents an operation pipeline control unit. The operation pipeline control unit 1 receives an arithmetic instruction from a control unit (not shown) and then subjects the entire operation unit including the operation units 7 and 9, and the FR 6 to a pipeline control. The operation pipeline control unit 1 includes an instruction queue 2, an instruction register 3, a decoder (DEC) 4, and a pipeline control circuit 5.
The instruction queue 2 holds an arithmetic instruction sent from a control unit (not shown). The instruction register 3 is selected by the pipeline control circuit 5 and then stores temporarily an arithmetic instruction read out of the instruction queue 2.
The decoder 4 decodes an arithmetic instruction stored in the instruction register 3 and then sends the decoded results as a register number to the FR 6, an instruction signal to operation units 7 and 9, and an arithmetic start signal to the pipeline operation unit 9.
The pipeline control circuit 5 issues an instruction selection signal to the instruction queue 2; issues an interlock signal in the register reading stage Ff to the decoder 4; and then controls the pipeline of the operation unit during the operation of the non-pipeline operation unit 7.
The FR 6 reads and stores data corresponding to the address designated by the operation pipeline control unit 1 and stores the operation result of the operation units 7 and 9.
The non-pipeline operation unit 7 such as a divider starts its arithmetic operation in response to an operation start signal from the operation pipeline control unit 1 (decoder 14). The pipeline operation unit 9 such as a multiplier can execute the above-mentioned pipeline operation and starts arithmetic operation when an operation start signal is received from the operation pipeline control unit 1 (decoder 4).
As shown in FIGS. 9(a)-9(c) after the non-pipeline operation unit 7 starts its operation (FIG. 9(a)), the pipeline operation unit 9 sharing the writing port 6a may start its arithmetic operation (FIG. 9(b)). In this case, after the completion of the instruction selection stage Sf, when the pipeline control circuit 5 outputs an interlock signal to the decoder 4, the pipeline operation unit 9 does not start its arithmetic operation because it is interlocked in the register reading stage Ff.
After the completion of the arithmetic operation of the non-pipeline operation unit 7, the operation result is written into the FR 6 in the writing stage Wf. Then the interlock state in the register reading stage Ff is released because the output of the interlock signal is stopped and then the pipeline operation unit 9 starts its arithmetic operation. Hence, the pipeline operation unit 9 waits for (n+1) xcfx84, where n is the number of operation cycles (the number of operation execution stages) of the non-pipeline operation unit 7 (FIG. 9(c)).
Next, the configuration of the pipeline operation device adopting the latter method (b) will be shown in FIG. 10. The pipeline operation device shown FIG. 10 is substantially identical to that shown in FIG. 8. However, the pipeline control circuit 5 in the pipeline operation device shown in FIG. 10 includes an interlock signal producing circuit 5A.
When the writing stage Wf of the non-pipeline operation unit 7 overlaps with the writing stage Wf of the pipeline operation unit 9, the interlock signal producing circuit 5A issues an interlock signal to the pipeline operation unit 9 in the writing stage Wf.
As shown in FIGS. 11(a)-11(c), while the non-pipeline operation unit 7 is operating (FIG. 11(a), the pipeline operation unit 9 sharing the writing port 6a executes an arithmetic operation (FIG. 11(b). In this case, when the writing stage Wf of the pipeline operation unit 9 overlaps with the writing stage Wf of the non-pipeline operation unit 7, the interlock signal producing circuit 5A issues an interlock signal to the pipeline operation unit 9 in the writing stage Wf of the non-pipeline operation unit 9 (FIG. 11(c).
When receiving an interlock signal, the pipeline operation unit 9 is interlocked, thus ceasing its operation in the writing stage Wf. After waiting for 1xcfx84 during which the non-pipeline operation unit 7 writes the operation result into the FR 6, the non-pipeline operation unit 7 releases the interlock state. Then the non-pipeline operation unit 7 writes the operation result of the pipeline operation unit 9 to the FR 6 in the writing stage Wf.
However, there has been a disadvantage in that since the conventional pipeline operation device adopting the former method (a) cannot use the pipeline operation unit 9 for the maximum term (n+1)xcfx84 during which the non-pipeline operation unit 7 completes a writing operation to the FR 6 in the writing stage Wf, the operation processing performance is remarkably reduced.
The conventional pipeline operation unit adopting the latter method (b) can resolve the above-mentioned problems. However, the mechanism which stops simultaneously pipelines in the pipeline operation unit 9 is needed to stop the pipeline operation unit 9 in the writing stage Wf. There has been a disadvantage in that adding the stop mechanism leads to complicated circuits and an increased number of components.
The present invention is made to overcome the above mentioned problems. An object of the present invention is to provide a pipeline operation method that can effectively write the operation results of plural operation units sharing a writing port merely by adding a simplified circuit, thus improving the performance of an operation process.
Another object of the present invention is to provide a pipeline operation device that can effectively write the operation results of plural operation units sharing a writing port merely by adding a simplified circuit, thus improving the performance of an operation process.
In order to achieve the above objects, according to the present invention, the pipeline operation method suitable to a system including a pipeline operation unit that can perform a pipeline operation, a non-pipeline operation unit that cannot perform a pipeline operation, and a register that is shared by the pipeline operation unit and the non-pipeline operation unit, performs an arithmetic operation while an operation result of each of the pipeline units is being written into the register, and includes the step of interlocking translating an instruction to the pipeline operation unit when a writing stage of an operation result from the pipeline operation unit is overlapped with a writing stage of an operation result from the non-pipeline operation unit.
According to the present invention, the pipeline operation device is characterized by a pipeline operation unit that can perform a pipeline operation; a non-pipeline operation unit that cannot perform a pipeline operation; a register that is shared by the pipeline operation unit and the non-pipeline operation unit; an operation pipeline control unit that controls the operation of each of the pipeline operation unit and the non-pipeline operation unit; the pipeline control unit controlling an operation of each of the operation units and performing an arithmetic operation while an operation result of each of the operation units is being written into the register; the operation pipeline control unit including an interlock execution unit that interlocks translating an instruction to the pipeline operation unit when a writing stage of an operation result of the pipeline operation unit overlaps with a writing stage of an operation result of the non-pipeline operation unit.
As described above, according to the pipeline operation method and the pipeline operation device, when the writing stage of the operation result of the pipeline operation unit overlaps with the writing stage of the operation result of the non-pipeline operation unit, the stage in which an instruction to the pipeline operation unit is translated is interlocked, whereby the operation process of the pipeline operation unit is temporarily postponed.
Therefore, each operation result is written to the register with the execution timing shifted between the writing stage of the operation result of the pipeline operation unit and the writing stage of the operation result of the non-pipeline operation unit. The operation results of plural operation units sharing a writing port can be effectively written into a register merely by adding a simplified circuit so that the arithmetic operation performance can be largely improved.